Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Phase-locked delay loop for clock correction

Phase-locked delay loop for clock correction

US Patent 5646564 · Granted Jul 8, 1997

Estimated economic value: $11,635,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Modular stacked silicon package assembly2022
Dispense verification meters2013
Dispense verification meters2012
Programmable memory controller2012
Power management with packaged multi-die integrated circuit2011
Expert system supported interactive product selection and recommendation2011
Expert supported interactive product selection and recommendation2009
High speed configurable transceiver architecture2007
Network physical layer with embedded multi-standard CRC generator2006
Expert system adapted dedicated internet access guidance engine2006
Expert system adapted data network guidance engine2004
Correlator method and apparatus2001