Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits

Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits

US Patent 5644251 · Granted Jul 1, 1997

Estimated economic value: $8,091,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Event based test method for debugging timing related failures in integrated circ2007
Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufactu2007
Dual-height cell with variable width power rail architecture2006
Event based IC test system2006
Method for design validation of complex IC2006
Method of evaluating core based system-on-a-chip (SoC) and structure of SoC inco2005
Method of evaluating core based system-on-a-chip2005
High speed vector access method from pattern memory for test systems2005
Dual-height cell with variable width power rail architecture2005
Calibration method for system performance validation of automatic test equipment2004
High speed semiconductor test system using radially arranged pin cards2004
Locking apparatus and loadboard assembly2004