Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Read and writable data bus particularly for programmable logic devices

Read and writable data bus particularly for programmable logic devices

US Patent 5635851 · Granted Jun 3, 1997

Estimated economic value: $24,814,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Configurable processor system unit2002
Encryption of configuration stream2001
Integrated circuit with field programmable and application specific logic areas2000
FPGA architecture with repeatable titles including routing matrices and logic ma1999
Integrated circuit with field programmable and application specific logic areas1998
Method and circuit for using a function generator of a programmable logic device1998
FPGA architecture with repeatable tiles including routing matrices and logic mat1997
I/O interface cell for use with optional pad1996
Programmable array logic cell1988
Buffered Miller current compensating circuit1987