Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architecture

Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architecture

US Patent 5611071 · Granted Mar 11, 1997

Estimated economic value: $8,711,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Rule-based virtual address translation for accessing data2016
Generating test input for a circuit2008
Method and system for providing clock signals2006
Method and system for synchronizing output from differently timed circuits2006
CPU-peripheral bus interface using byte enable signaling to control byte lane st2000
I/O bus interface recovery counter dependent upon minimum bus clocks to prevent 1999
Coherency for write-back cache in a system designed for write-through cache incl1999
Microprocessor having a compensated input buffer circuit1998
Coherency for write-back cache in a system designed for write-through cache usin1997
Single clock bus transfers during burst and non-burst cycles1997
Coherency for write-back cache in a system designed for write-through cache incl1996