Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Parallel architecture error correction and conversion system

Parallel architecture error correction and conversion system

US Patent 5588010 · Granted Dec 24, 1996

Estimated economic value: $38,165,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatus and method for built-in test and repair of 3D-IC memory2017
Secure debug interface and memory of a media security circuit and method2012
Method and apparatus for providing a modular system on-chip interface2004
Virtual component on-chip interface2002
Methods and apparatus for processing video data2001
Shared bus system with transaction and destination ID2001
System and method for controlling the direction of data flow between computing e1999
Simultaneous data transfer through read and write buffers of a DMA controller1999
Priority request and bypass bus1999
DMA controller which receives size data for each DMA channel1999
Byte-writable two-dimensional FIFO buffer having storage locations with fields i1999
DMA controller with channel tagging1999