Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits

Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits

US Patent 5517147 · Granted May 14, 1996

Estimated economic value: $4,465,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic load balancing for multi-core computing environments2025
Hardware queue scheduling for multi-core computing environments2025
Dynamic load balancing for multi-core computing environments2025
Work conserving, load balancing, and scheduling2023
Dynamic load balancing for multi-core computing environments2023
Techniques for processor queue management2021
Multi-core communication acceleration using hardware queue device2021
Work conserving, load balancing, and scheduling2020
Multi-core communication acceleration using hardware queue device2019
Method and apparatus for dynamically balancing task processing while maintaining2019
Technologies for a distributed hardware queue manager2019
Network processor having multicasting protocol2018