Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution

Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution

US Patent 5488729 · Granted Jan 30, 1996

Estimated economic value: $9,887,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Delivering and displaying advertisement or other application data to display sys2016
Data streamer2009
Integrated multimedia system2008
Integrated multimedia system2007
Processing circuit and method for variable-length coding and decoding2007
Data transfer engine of a processor having a plurality of modules2006
Processing circuit and method for variable-length coding and decoding2003
Data cache system2003
Processing circuit and method for variable-length coding and decoding2003
Data streamer2002
Integrated multimedia system with local processor, data transfer switch, process2002
Processor which performs dynamic instruction scheduling at time of execution wit1999