Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9525850 | Delivering and displaying advertisement or other application data to display systems | Amit Jain, Roger A. Hajjar | 2016-12-20 |
| 7548996 | Data streamer | David Poole, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee +5 more | 2009-06-16 |
| 7457890 | Integrated multimedia system | David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio +9 more | 2008-11-25 |
| 7272670 | Integrated multimedia system | David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio +9 more | 2007-09-18 |
| 7262720 | Processing circuit and method for variable-length coding and decoding | Richard Deeley, Woobin Lee | 2007-08-28 |
| 7051123 | Data transfer engine of a processor having a plurality of modules | David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee +5 more | 2006-05-23 |
| 6587058 | Processing circuit and method for variable-length coding and decoding | Richard Deeley, Woobin Lee | 2003-07-01 |
| 6560674 | Data cache system | Koji Hosogi, Gregorio Gervasio, Radhika Thekkath | 2003-05-06 |
| 6507293 | Processing circuit and method for variable-length coding and decoding | Richard Deeley, Woobin Lee | 2003-01-14 |
| 6434649 | Data streamer | David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee +6 more | 2002-08-13 |
| 6347344 | Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor | David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio +9 more | 2002-02-12 |
| 5884060 | Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle | Anantakotiraju Vegesna, Jayachandra B. Avula, Peter H. Jewett, Vinay Naik, James E. Monaco | 1999-03-16 |
| 5640588 | CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle | Anantakotiraju Vegesna, Jayachandra B. Avula, Peter H. Jewett, Vinay Naik, James E. Monaco | 1997-06-17 |
| 5488729 | Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution | Anantakotiraju Vegesna, Jayachandra B. Avula, Peter H. Jewett | 1996-01-30 |
| 5459673 | Method and apparatus for optimizing electronic circuits | Douglas M. Carmean | 1995-10-17 |