Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of fabricating self aligned semiconductor devices

Method of fabricating self aligned semiconductor devices

US Patent 4883767 · Granted Nov 28, 1989

Estimated economic value: $10,890,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Power devices having tunable saturation current clamps therein that support impr2024
Power MOSFET and JBSFET cell topologies with superior high frequency figure of m2022
Monolithically-integrated AC switch having JBSFETs therein with commonly-connect2020
Power MOSFETs with superior high frequency figure-of-merit2019
Semiconductor including cup-shaped leadframe packaging techniques2015
Integrated circuit package for semiconductior devices with improved electric res2012
Integrated circuit package for semiconductor devices with improved electric resi2011
Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filt2011
Inverted J-lead for power devices2009
Semiconductor die package including cup-shaped leadframe2009
Integrated circuit package for semiconductor devices having a reduced leadframe 2008
Power semiconductor package2007