Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective subtraction procedure

Apparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective subtraction procedure

US Patent 4852039 · Granted Jul 25, 1989

Estimated economic value: $18,226,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Extension of openvswitch megaflow offloads to hardware to address hardware pipel2025
Technologies that provide policy enforcement for resource access2024
Vector friendly instruction format and execution thereof2024
Vector friendly instruction format and execution thereof2023
Vector friendly instruction format and execution thereof2021
Vector friendly instruction format and execution thereof2020
Virtual group policy based filtering within an overlay network2018
Instruction and logic to provide vector blend and permute functionality2018
Double rounded combined floating-point multiply and add2017
Vector friendly instruction format and execution thereof2016
Double rounded combined floating-point multiply and add2016
Combined floating point multiplier adder with intermediate rounding logic2016