Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory array biasing circuit for high speed CMOS device

Memory array biasing circuit for high speed CMOS device

US Patent 4636983 · Granted Jan 13, 1987

Estimated economic value: $4,024,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Vertical cross-point arrays for ultra-high-density memory applications2023
3D memory array clusters and resulting memory architecture2023
Vertical cross-point arrays for ultra-high-density memory applications2022
3D memory array clusters and resulting memory architecture2021
Thyristor volatile random access memory and methods of manufacture2021
Global bit line pre-charge circuit that compensates for process, operating volta2021
Food storage appliance2020
Vertical cross-point arrays for ultra-high-density memory applications2020
Reduced current memory device2020
Global bit line pre-charge circuit that compensates for process, operating volta2020
High-speed data transfer periods for thyristor memory cell arrays2020
Thyristor volatile random access memory and methods of manufacture2020