{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Monolithic CMOS low power digital level shifter", "item": "https://www.patentleaderboard.com/patent/4486670"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Monolithic CMOS low power digital level shifter

Monolithic CMOS low power digital level shifter

US Patent 4486670 · Granted Dec 4, 1984

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electronic devices with ultraviolet blocking layers2014
Low-H plasma treatment with N2 anneal for electronic memory devices2012
Method of forming an electronic device2012
Delay locked loop circuitry for clock delay adjustment2007
Delay locked loop circuitry for clock delay adjustment2006
Control mechanism for matching process parameters in a multi-chamber process too2004
Method for preventing or reducing delamination of deposited insulating layers2003
Method and system for controlling the plasma treatment of a titanium nitride lay2003
Delay locked loop circuitry for clock delay adjustment2003
Method of reducing interlayer dielectric thickness variation feeding into a plan2003
Method and apparatus for reducing deposition variation by modeling post-clean ch2003
Method and apparatus for determining measurement frequency based on hardware age2002