Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Droop mitigation for an inter-chiplet interface

Droop mitigation for an inter-chiplet interface

US Patent 12147366 · Granted Nov 19, 2024

Estimated economic value: $1,120,501,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Arbitrated interrupt steering in heterogeneous processors2025
Memory power performance state optimization during image display2025
Method of task transition between heterogenous processors2025
Reduced mesh lane routing2025
On-demand regulation of memory bandwidth utilization to service requirements of 2025
Low power memory state during non-idle processor state2025
Mechanism for performing distributed power management of a multi-GPU system by p2025
System-wide low power management2025
Scheduling training of an inter-chiplet interface2025
Scheduling training of an inter-chiplet interface2025
On-demand IP initialization within power states2025
Device and method for two-stage transitioning between reduced power states2025