Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system

Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system

US Patent 12093186 · Granted Sep 17, 2024

Estimated economic value: $317,734,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Treating main memory as a collection of tagged cache lines for trace logging2025
Cache-line retention hint information for conditional write instruction2025
Method, apparatus, and system for storing memory encryption realm key IDs2024
Efficiently replacing software breakpoint instructions in processor-based device2024
Tracking memory block access frequency in processor-based devices2024
Obsoleting values stored in registers in a processor based on processing obsoles2023
Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for aug2023
Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for aug2023
Method, apparatus, and system for storing memory encryption realm key IDs2023
Performing speculative address translation in processor-based devices2023
Cache-based trace logging using tags in an upper-level cache2023
Combining load or store instructions2023