Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › IC structure including porous semiconductor layer under trench isolation

IC structure including porous semiconductor layer under trench isolation

US Patent 12027582 · Granted Jul 2, 2024

Estimated economic value: $39,583,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Isolation stack for a bipolar transistor and related methods2025
Bipolar transistor2025
Field effect transistor with shallow trench isolation features within source/dra2025
Field effect transistor with shallow trench isolation features within source/dra2025
Field effect transistor with shallow trench isolation features within source/dra2025
Heterojunction bipolar transistor with buried trap rich isolation region2025
Heterojunction bipolar transistor with buried trap rich isolation region2025
High electron mobility transistors having barrier liners and integration schemes2025
Structure including grating coupler with optofluidic grating channels2025
Photodiodes2025
Electro-absorption modulators with stacked waveguide tapers2025
Contact-over-active-gate transistor structures with contacts landed on enlarged 2025