Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Processor implementing parallel in-order execution during load misses

Processor implementing parallel in-order execution during load misses

US Patent 12001847 · Granted Jun 4, 2024

Estimated economic value: $189,142,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Remote cache invalidation2025
Coprocessor operation bundling2025
Atomic operation predictor to predict whether an atomic operation will complete 2025
Storage array invalidation maintenance2024
Atomic operation predictor to predict whether an atomic operation will complete 2024
Virtual channel support using write table2024
Real-time processing in computer systems2024
Real-time processing in computer systems2024
Coprocessor operation bundling2023
Storage array invalidation maintenance2023
Processor with reduced interrupt latency2023
Processor with reduced interrupt latency2023