{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Non-planar transistor arrangements with asymmetric gate enclosures", "item": "https://www.patentleaderboard.com/patent/11984487"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Non-planar transistor arrangements with asymmetric gate enclosures

Non-planar transistor arrangements with asymmetric gate enclosures

US Patent 11984487 · Granted May 14, 2024

Estimated economic value: $33,809,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Stitching to enable dense interconnect arrangements2025
Power rail between fins of a transistor structure2025
Gate-all-around integrated circuit structures having germanium-diffused nanoribb2025
Source/drain regions in integrated circuit structures2025
Source/drain regions in integrated circuit structures2025
Source/drain regions in integrated circuit structures2025
Asymmetric gate structures and contacts for stacked transistors2025
3D 1T1C stacked dram structure and method to fabricate2025
Gate spacing in integrated circuit structures2025
Gate spacing in integrated circuit structures2025
Self-aligned lateral contacts2025
Transistor with isolation below source and drain2025