Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications

Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications

US Patent 11967960 · Granted Apr 23, 2024

Estimated economic value: $518,701,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems and methods for serialized initialization circuitry2025
System and method for controlling power consumption in processor using interconn2025
Apparatus and methods employing asynchronous FIFO buffer with read prediction2024
Apparatus and methods employing asynchronous FIFO buffer with read prediction2024
Low power single phase logic gate latch for clock-gating2024
Multi-chiplet clock delay compensation2024
System and method for controlling electrical current supply in a multi-processor2023
System and method for enabling clock stretching during overclocking in response 2023
Power on die discovery in 3D stacked die architectures with varying number of st2023
Method and apparatus for synchronizing the time stamp counter2023
Method and apparatus for synchronizing the time stamp counter2023
Level-based droop detection2023