Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods and apparatuses for addressing memory caches

Methods and apparatuses for addressing memory caches

US Patent 11921642 · Granted Mar 5, 2024

Estimated economic value: $20,778,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High bandwidth memory system2025
Two-dimensional processing array with a vertically stacked memory tile array2025
Programmable access engine architecture for graph neural network and graph appli2025
Scaling out architecture for dram-based processing unit (DPU)2025
Graph acceleration solution with cloud FPGA2025
Hybrid solid state drive (SSD) architecture using MRAM and NAND for improved pow2025
Effective transaction table with page bitmap2025
Computing system for implementing artificial neural network models and method fo2025
Systems and methods for memory bandwidth allocation2025
Bandwidth boosted stacked memory2025
DRAM assist error correction mechanism for DDR SDRAM interface2025
Methods and apparatuses for addressing memory caches2025