Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Failure-tolerant error correction layout for memory sub-systems

Failure-tolerant error correction layout for memory sub-systems

US Patent 11870461 · Granted Jan 9, 2024

Estimated economic value: $10,439,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory read calibration based on memory device-originated metrics characterizing2025
Multi-stage bit line pre-charge2025
Method for improving control gate uniformity during manufacture of processors wi2025
Semiconductor packages and methods of manufacturing thereof2025
Device and method for UBM/RDL routing2025
Modification of program voltage level with read or program-verify adjustment for2025
Moveable gripper for gripping a container and heating contents of the container 2025
Method to embed planar FETs with finFETs2025
Wafer bonding method and bonded device structure2025
Monitoring memory device health according to data storage metrics2025
Bonded wafer device structure and methods for making the same2025
Semiconductor device and manufacturing method thereof2025