Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuit for generating and trimming phases for memory cell read operations

Circuit for generating and trimming phases for memory cell read operations

US Patent 11798603 · Granted Oct 24, 2023

Estimated economic value: $20,570,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Voltage regulator comprising a charge pump circuit2025
Methods, systems, and devices for spectrally adjusting audio gain in videoconfer2025
Voltage regulator circuit for a switching circuit load2025
Non-volatile memory cell with single poly, floating gate extending over two well2024
Device and method to generate bias voltages in non-volatile memory2024
Circuit and method for on-chip leakage detection and compensation for memories2024
Voltage regulator circuit for a switching circuit load2024
Memory circuit arrangement for accurate and secure read2024
Deformable electronic device with deformation estimation system and correspondin2024
Generating content feed based on policy associated with adjacent content2024
Circuit and method to detect word-line leakage and process defects in non-volati2024
Circuit and method to detect word-line leakage and process defects in non-volati2024