Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Clock mapping in an integrated circuit design

Clock mapping in an integrated circuit design

US Patent 11663381 · Granted May 30, 2023

Estimated economic value: $4,328,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System for collaborative hardware RTL logic timing debug in integrated circuit d2025
Semiconductor device including insulated gate bipolar transistor2025
Logical clock connection in an integrated circuit design2025
Logical clock connection in an integrated circuit design2025
Logical clock connection in an integrated circuit design2025
Logical clock connection in an integrated circuit design2025
Logical clock connection in an integrated circuit design2025
Logical clock connection in an integrated circuit design2025
Logical clock connection in an integrated circuit design2025
Centralized distribution of multicast requests in a data processing system2024
Memory migration within a multi-host data processing environment2024
Signal pre-routing in an integrated circuit design2024