Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory device implementing multiple port read

Memory device implementing multiple port read

US Patent 11367480 · Granted Jun 21, 2022

Estimated economic value: $47,078,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Bitline-driven sense amplifier clocking scheme2020
Providing efficient handling of memory array failures in processor-based systems2020
Method and apparatus of reducing leakage power in multiple port SRAM memory cell2014
SRAM cell writability2014
Apparatus for selective word-line boost on a memory cell2014
Adaptive read wordline voltage boosting apparatus and method for multi-port SRAM2014
Low leakage high performance static random access memory cell using dual-technol2013
Low leakage high performance static random access memory cell using dual-technol2011
Content addressable memory2011
High speed CAM lookup using stored encoded key2010
Method and apparatus for reducing power consumption in a content addressable mem2009
Method and apparatus for aborting content addressable memory search operations2009