Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High density low power interconnect using 3D die stacking

High density low power interconnect using 3D die stacking

US Patent 11233002 · Granted Jan 25, 2022

Estimated economic value: $169,177,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High density low power interconnect using 3D die stacking2024
High density low power interconnect using 3D die stacking2024
Dendritic polypeptide-based nanocarriers for the delivery of therapeutic agents2018
Memory optimization in VLSI design using generic memory models2017
Generating specific memory models using generic memory models for designing memo2017
Designing memories in VLSI design using specific memory models generated from ge2017
Scaling logic components of integrated circuit design2016
Scaling logic components of integrated circuit design2016
Scaling of integrated circuit design including logic and memory components2016
Scaling of integrated circuit design including logic and memory components2016
Integrated circuit design scaling for recommending design point2016
Integrated circuit design scaling for recommending design point2016