Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designs

Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designs

US Patent 11201610 · Granted Dec 14, 2021

Estimated economic value: $17,774,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Logic cell structures and related methods2025
Logic cell structures and related methods2023
Tapering discrete interconnection for an integrated circuit (IC)2022
Tapering discrete interconnection for an integrated circuit (IC)2022
Selectable delay buffers and logic cells for dynamic voltage scaling in ultra lo2020
Selectable delay buffers and logic cells for dynamic voltage scaling in ultra lo2020
Tapering discrete interconnection for an integrated circuit (IC)2020
Tapering discrete interconnection for an integrated circuit (IC)2020
Techniques based on electromigration characteristics of cell interconnect2020
Selectable delay buffers and logic cells for dynamic voltage scaling in ultra lo2019
Selectable delay buffers and logic cells for dynamic voltage scaling in ultra lo2019
Tapering discrete interconnection for an integrated circuit (IC)2019