Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programming process combining adaptive verify with normal and slow programming speeds in a memory device

Programming process combining adaptive verify with normal and slow programming speeds in a memory device

US Patent 11017869 · Granted May 25, 2021

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Program refresh with gate-induced drain leakage2025
Dual-way sensing scheme for better neighboring word-line interference2025
Memory program-verify with adaptive sense time based on row location2025
Evolving bad block detection in non-volatile memory2025
Open block read ICC reduction2025
Suspend-resume-go techniques for memory devices2025
Memory die management2025
In-place write techniques without erase in a memory device2025
Estimating moving vehicle weight based on driving data2025
Large-scale text data encoding and compression2025
Corrective reads with improved recovery from data retention loss2025
Enabling significant scaling of wordline switch with wordline dependent negative2025