Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High performance regularized network-on-chip architecture

High performance regularized network-on-chip architecture

US Patent 10922471 · Granted Feb 16, 2021

Estimated economic value: $35,223,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hazard mitigation for lightweight processor cores2025
Hazard mitigation for lightweight processor cores2025
FPGA specialist processing block for machine learning2025
Vector processor architectures2025
Vector processor architectures2025
Programmable logic device with fine-grained disaggregation2025
Rank-based dot product circuitry2025
High precision decomposable DSP entity2024
Systems and methods for low latency modular multiplication2024
Programmable integrated circuit underlay2024
Programmable integrated circuit underlay2024
Efficient dual-path floating-point arithmetic operators2024