Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor device and semiconductor wafer including a porous layer and method of manufacturing

Semiconductor device and semiconductor wafer including a porous layer and method of manufacturing

US Patent 10714377 · Granted Jul 14, 2020

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method of manufacturing a semiconductor device2025
Semiconductor device including a field stop region2025
Method of manufacturing a metal silicide layer above a silicon carbide substrate2025
Method for producing a superjunction device2025
Power semiconductor device having an electrode with an embedded material2025
Method of manufacturing ohmic contacts on a silicon carbide (SIC) substrate, met2025
Semiconductor device including a field stop region2025
Transistor device and method of manufacturing2025
Transistor device and method of manufacturing2025
Semiconductor device with a porous portion, wafer composite and method of manufa2025
Semiconductor device with a porous portion, wafer composite and method of manufa2025
Semiconductor device with a porous portion, wafer composite and method of manufa2025