Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Transistors and methods of forming transistors using vertical nanowires

Transistors and methods of forming transistors using vertical nanowires

US Patent 10658494 · Granted May 19, 2020

Estimated economic value: $54,061,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Vertically stacked cascode bipolar junction transistor (BJT) pair sensor2025
Stacked complementary field effect transistors2025
Power distribution network with backside power rail2025
Tunnel field effect transistor devices2025
Forksheet transistor with dual depth late cell boundary cut2025
Hybrid stacked field effect transistors2025
Gate induced drain leakage reduction in FinFETs2025
Textured cobalt aluminum/magnesium-aluminum-oxide pedestal for memory devices2025
Semiconductor device with void under source/drain region for backside contact2025
Epi growth uniformity with source/drain placeholder2025
VTFET with controlled fin height2025
Nanowire source/drain formation for nanosheet device2025