Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for alignment, process tool and method for wafer-level alignment

Method for alignment, process tool and method for wafer-level alignment

US Patent 10636688 · Granted Apr 28, 2020

Estimated economic value: $7,447,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Mechanical wafer alignment detection for bonding process2025
Physical distancing tracking and notification2025
Semiconductor structure having a silicon active layer formed over a SiGe etch st2025
Apparatus and method for wafer bonding2025
Apparatus and method for wafer bonding2025
Semiconductor-on-insulator wafer having a composite insulator layer2025
Ring cover2025
Structure for embedded gettering in a silicon on insulator wafer2025
Conductive contact for ion through-substrate via2025
Ring cover2025
Method of optimizing film deposition process in semiconductor fabrication by usi2025
3D trench capacitor for integrated passive devices2025