Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reuse of extracted layout-dependent effects for circuit design using circuit stencils

Reuse of extracted layout-dependent effects for circuit design using circuit stencils

US Patent 10521535 · Granted Dec 31, 2019

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Computing parasitic values for semiconductor designs2025
Methods and systems to determine parasitics for semiconductor or flat panel disp2025
Generating and display an animation of a predicted overlap shape in an IC design2025
Computing parasitic values for semiconductor designs2025
Methods and systems to determine shapes for semiconductor or flat panel display 2025
Full correlation aging analysis over combined process voltage temperature variat2023
Creating and reusing customizable structured interconnects2021
Extreme cases sampling method for improved variation-aware full custom design2021
Full-custom voltage-dependent design rules (VDRC) flow2020
Hierarchical dynamic heat maps in full custom EDA applications2020
Creating and reusing customizable structured interconnects2020
Integrated circuit design using generation and instantiation of circuit stencils2019