Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387029 | Computing parasitic values for semiconductor designs | Akira Fujimura, Nagesh Shirali | 2025-08-12 |
| 12372864 | Methods and systems to determine shapes for semiconductor or flat panel display fabrication | Akira Fujimura, Nagesh Shirali | 2025-07-29 |
| 11790127 | Full correlation aging analysis over combined process voltage temperature variation | — | 2023-10-17 |
| 10896274 | Extreme cases sampling method for improved variation-aware full custom design | Guy M. Morency, Jonathan Lee Sanders | 2021-01-19 |
| 10796062 | Full-custom voltage-dependent design rules (VDRC) flow | Nabil Yazdani, Jingyu Xu, Bulent Basaran, Larissa Nitchougovskaia | 2020-10-06 |
| 10719650 | Hierarchical dynamic heat maps in full custom EDA applications | Jonathan Lee Sanders, Salem Lee Ganzhorn, Yevgenia Murad Beglaryan, Liana Badalyan | 2020-07-21 |
| 10521535 | Reuse of extracted layout-dependent effects for circuit design using circuit stencils | Friedrich Gunter Kurt Sendig | 2019-12-31 |
| 10380297 | Integrated circuit design using generation and instantiation of circuit stencils | Friedrich Gunter Kurt Sendig, Jonathan Lee Sanders, Salem Lee Ganzhorn, Barry A. Giffel, Hsiang-Wen Jimmy Lin | 2019-08-13 |
| 10242139 | Scheme and design markup language for interoperability of electronic design application tool and browser | Salem Lee Ganzhorn | 2019-03-26 |
| 10242135 | Testbench chaining for multiple blocks in hierarchical circuit design | Gajanan Madhukarrao Joshi, Jonathan Lee Sanders, Ruben Grigoryan, Hui Xu | 2019-03-26 |
| 10102324 | Reuse of extracted layout-dependent effects for circuit design using circuit stencils | Friedrich Gunter Kurt Sendig | 2018-10-16 |
| 10078715 | Integrated circuit design using generation and instantiation of circuit stencils | Friedrich Gunter Kurt Sendig, Jonathan Lee Sanders, Salem Lee Ganzhorn, Barry A. Giffel, Hsiang-Wen Jimmy Lin | 2018-09-18 |