{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Selectable trim settings on a memory device", "item": "https://www.patentleaderboard.com/patent/10431319"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Selectable trim settings on a memory device

Selectable trim settings on a memory device

US Patent 10431319 · Granted Oct 1, 2019

Estimated economic value: $10,821,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Trim setting determination on a memory device2025
Trim setting determination on a memory device2025
Trim setting determination on a memory device2025
Buffer allocation for reducing block transit penalty2025
Multiple-pass programming of memory cells using temporary parity generation2025
Using a common pool of blocks for user data and a system data structure2025
Voltage bin calibration based on a voltage distribution reference voltage2025
Trim setting determination for a memory device2025
Trim setting determination for a memory device2025
Trim setting determination for a memory device2025
Management of error-handling flows in memory devices using probability data stru2025
Block family-based error avoidance for memory devices2025