Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Fused-multiply-add floating-point operations on 128 bit wide operands

Fused-multiply-add floating-point operations on 128 bit wide operands

US Patent 10303438 · Granted May 28, 2019

Estimated economic value: $2,255,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clamping means for a light guide element and light guide element arrangement wit2025
Vector test decimal instruction for validity testing2025
Hardware-based implementation of secure hash algorithms2025
Hardware-based message block padding for hash algorithms2025
Method and system for calibrating a controller of an engine2024
Dispatching multiply and accumulate operations based on accumulator register ind2024
Method for producing rotationally symmetrical, non-cylindrical bores with a honi2024
Heat exchanger and cooling method2024
Exhaust muffler2023
Enhanced low precision binary floating-point formatting2023
Compute array of a processor with mixed-precision numerical linear algebra suppo2023
Compute array of a processor with mixed-precision numerical linear algebra suppo2023