Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design

Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design

US Patent 10275554 · Granted Apr 30, 2019

Estimated economic value: $36,471,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Responding to unsupported or degraded conditions for autonomous vehicles2024
Circuit design modification using timing-based yield calculation2024
Cell instance charge model for delay calculation2023
Reinforcement learning-based adjustment of digital circuits2023
Method, system, and product for deferred merge based method for graph based anal2021
Methods, systems, and computer program product for characterizing an electronic 2021
Methods, systems, and computer program product for characterizing timing behavio2021
Analyzing clock jitter using delay calculation engine2021
Characterizing electronic component parameters including on-chip variations and 2020
Method and apparatus for yield calculation using statistical timing data that ac2019
Method and apparatus for yield calculation using statistical timing data that ac2019
Method and apparatus for yield calculation using statistical timing data that ac2019