Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies

Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies

US Patent 10268122 · Granted Apr 23, 2019

Estimated economic value: $25,127,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Cladding layer epitaxy via template engineering for heterogeneous integration on2020
Selective epitaxially grown III-V materials based devices2020
Making a defect free fin based device in lateral epitaxy overgrowth region2019
Non-silicon device heterolayers on patterned silicon substrate for CMOS by combi2019
Techniques for forming a compacted array of functional cells2019
Techniques for forming a compacted array of functional cells2019
Selective epitaxially grown III-V materials based devices2019
Methods and structures to prevent sidewall defects during selective epitaxy2018
Decoupling capacitors and arrangements2018
Decoupling capacitors and arrangements2018
Self-aligned structures and methods for asymmetric GaN transistors and enhanceme2018
GE and III-V channel semiconductor devices having maximized compliance and free 2018