Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof

Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof

US Patent 10032908 · Granted Jul 24, 2018

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Current source for read of programmable resistance memory cells2025
One-time programmable memory devices and methods2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensio2025
Quasi-volatile memory with reference bit line structure2025
Overwrite read methods for resistance switching memory devices2025
Three-dimensional memory string array of thin-film ferroelectric transistors2024
Semiconductor memory device with write disturb reduction2024
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2024
Memory device including modular memory units and modular circuit units for concu2024
First fire and cold start in memories with threshold switching selectors2024
3-dimensional memory string array of thin-film ferroelectric transistors2023