Issued Patents All Time
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6594808 | Structural regularity extraction and floorplanning in datapath circuits using vectors | Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh Sehgal | 2003-07-15 |
| 6152612 | System and method for system level and circuit level modeling and design simulation using C++ | Stan Liao, Steve Tjiang | 2000-11-28 |
| 6148433 | Systematic approach for regularity extraction | Amit Chowdhary, Sudhakar Kale, Phani Saripella, Naresh Sehgal | 2000-11-14 |
| 5774368 | Controller structure template and method for designing a controller structure | Chih-Tung Chen, Kayhan Kucukcakar, Thomas E. Tkacik | 1998-06-30 |
| 5731985 | Chip sizing for hierarchical designs | John Sayah | 1998-03-24 |
| 5600567 | Method of graphically displaying and manipulating clock-based scheduling of HDL statements | Kayhan Kucukcakar, Thomas E. Tkacik | 1997-02-04 |
| 5533179 | Apparatus and method of modifying hardware description language statements | Kayhan Kucukcakar, Thomas E. Tkacik | 1996-07-02 |
| 5475607 | Method of target generation for multilevel hierarchical circuit designs | Jitendra Apte | 1995-12-12 |
| 4985640 | Apparatus for generating computer clock pulses | Edward T. Grochowski | 1991-01-15 |