Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12278636 | Receiver circuit with automatic DC offset cancellation in display port applications | Hongquan Wang, Shengyuan Zhang, Qing Chen, Liang Xu | 2025-04-15 |
| 12052020 | Methods and systems for controlling frequency and phase variations for PLL reference clocks | Hongquan Wang, Liang Chuan Chang, Liang Xu | 2024-07-30 |
| 12040804 | Methods and systems for controlling frequency variation for a PLL reference clock | Yiting Chen, Cindy Cheng, Hongquan Wang, Liang Chuan Chang | 2024-07-16 |
| 9209818 | On die jitter tolerance test | Ming Qu, Yuanping Chen, Yuntao Zhu, Quan Yu | 2015-12-08 |
| 8982932 | Active auxiliary channel buffering | Ming Qu, Zhengyu Yuan | 2015-03-17 |
| 8923375 | On die jitter tolerance test | Ming Qu, Yuanping Chen, Yuntao Zhu, Quan Yu | 2014-12-30 |
| 8610479 | On die low power high accuracy reference clock generation | Quan Yu, Yuntao Zhu, Lei Xie, Ming Qu | 2013-12-17 |
| 8144625 | DisplayPort auxiliary channel active buffer with auxiliary channel/display data channel combiner for fast auxiliary channel | Ming Qu, Zhengyu Yuan | 2012-03-27 |
| 7196551 | Current mode logic buffer | — | 2007-03-27 |
| 6680625 | Symmetrical CML logic gate system | Ming Qu, Xueping Jiang, Xiang Zhu | 2004-01-20 |
| 6614291 | Low voltage, high speed CMOS CML latch and MUX devices | Ji-Cheng Zhao, Edwin Chan | 2003-09-02 |
| 6429692 | High speed data sampling with reduced metastability | Edwin Chan, Ji-Cheng Zhao | 2002-08-06 |