Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8914690 | Multi-core processor having disabled cores | Martin Vorbach | 2014-12-16 |
| RE45223 | Method of self-synchronization of configurable elements of a programmable module | Martin Vorbach | 2014-10-28 |
| RE45109 | Method of self-synchronization of configurable elements of a programmable module | Martin Vorbach | 2014-09-02 |
| 8819505 | Data processor having disabled cores | Martin Vorbach | 2014-08-26 |
| RE44383 | Method of self-synchronization of configurable elements of a programmable module | Martin Vorbach | 2013-07-16 |
| RE44365 | Method of self-synchronization of configurable elements of a programmable module | Martin Vorbach | 2013-07-09 |
| 8195856 | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures | Martin Vorbach | 2012-06-05 |
| 8156312 | Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units | Martin Vorbach | 2012-04-10 |
| 7899962 | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures | Martin Vorbach | 2011-03-01 |
| 7822881 | Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like) | Martin Vorbach | 2010-10-26 |
| 7822968 | Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs | Martin Vorbach | 2010-10-26 |
| 7650448 | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures | Martin Vorbach | 2010-01-19 |
| 7584390 | Method and system for alternating between programs for execution by cells of an integrated circuit | Martin Vorbach | 2009-09-01 |
| 7565525 | Runtime configurable arithmetic and logic cell | Martin Vorbach | 2009-07-21 |
| 7337249 | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures | Martin Vorbach | 2008-02-26 |
| 7243175 | I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures | Martin Vorbach | 2007-07-10 |
| 7237087 | Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells | Martin Vorbach | 2007-06-26 |
| 7174443 | Run-time reconfiguration method for programmable units | Martin Vorbach | 2007-02-06 |
| 7036036 | Method of self-synchronization of configurable elements of a programmable module | Martin Vorbach | 2006-04-25 |
| 7028107 | Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) | Martin Vorbach | 2006-04-11 |
| 7010667 | Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity | Martin Vorbach | 2006-03-07 |
| 6990555 | Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) | Martin Vorbach | 2006-01-24 |
| 6968452 | Method of self-synchronization of configurable elements of a programmable unit | Martin Vorbach | 2005-11-22 |
| 6728871 | Runtime configurable arithmetic and logic cell | Martin Vorbach | 2004-04-27 |
| 6721830 | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures | Martin Vorbach | 2004-04-13 |