Issued Patents All Time
Showing 1–25 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12293193 | Advanced processor architecture | — | 2025-05-06 |
| 11797474 | High performance processor | — | 2023-10-24 |
| 11687346 | Providing code sections for matrix of arithmetic logic units in a processor | — | 2023-06-27 |
| 11061682 | Advanced processor architecture | — | 2021-07-13 |
| 10908914 | Issuing instructions to multiple execution units | Frank May, Markus Weinhardt | 2021-02-02 |
| 10885996 | Processor having a programmable function unit | — | 2021-01-05 |
| 10579584 | Integrated data processing core and array data processor and method for processing algorithms | Jürgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May | 2020-03-03 |
| 10409765 | Method for providing subapplications to an array of ALUs | Armin Nückel | 2019-09-10 |
| 10409608 | Issuing instructions to multiple execution units | Frank May, Markus Weinhardt | 2019-09-10 |
| 10331194 | Methods and devices for treating and processing data | Volker Baumgarte | 2019-06-25 |
| 10331615 | Optimization of loops and data flow sections in multi-core processor environment | — | 2019-06-25 |
| 10296488 | Multi-processor with selectively interconnected memory units | — | 2019-05-21 |
| 10152320 | Method of transferring data between external devices and an array processor | Volker Baumgarte, Frank May, Armin Nückel | 2018-12-11 |
| 10031888 | Parallel memory systems | — | 2018-07-24 |
| 10031733 | Method for processing data | Frank May, Markus Weinhardt, Joao Manuel Paiva Cardoso | 2018-07-24 |
| 9898297 | Issuing instructions to multiple execution units | Frank May, Markus Weinhardt | 2018-02-20 |
| 9817790 | Multi-processor with selectively interconnected memory units | — | 2017-11-14 |
| 9734064 | System and method for a cache in a multi-core processor | — | 2017-08-15 |
| 9703538 | Tool-level and hardware-level code optimization and respective hardware modification | — | 2017-07-11 |
| 9690747 | Configurable logic integrated circuit having a multidimensional structure of configurable elements | Armin Nückel | 2017-06-27 |
| 9672188 | Optimization of loops and data flow sections in multi-core processor environment | — | 2017-06-06 |
| 9626325 | Array processor having a segmented bus system | Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel +3 more | 2017-04-18 |
| 9552047 | Multiprocessor having runtime adjustable clock and clock dependent power supply | Volker Baumgarte | 2017-01-24 |
| 9436631 | Chip including memory element storing higher level memory data on a page by page basis | — | 2016-09-06 |
| 9411532 | Methods and systems for transferring data between a processing device and external devices | Volker Baumgarte, Frank May, Armin Nückel | 2016-08-09 |