Issued Patents All Time
Showing 101–125 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7210129 | Method for translating programs for reconfigurable architectures | Frank May, Armin Nückel | 2007-04-24 |
| 7174443 | Run-time reconfiguration method for programmable units | Robert Münch | 2007-02-06 |
| 7036036 | Method of self-synchronization of configurable elements of a programmable module | Robert Münch | 2006-04-25 |
| 7028107 | Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) | Robert Münch | 2006-04-11 |
| 7010667 | Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity | Robert Münch | 2006-03-07 |
| 7003660 | Pipeline configuration unit protocols and communication | Volker Baumgarte, Gerd Ehlers, Frank May, Armin Nückel | 2006-02-21 |
| 6990555 | Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) | Robert Münch | 2006-01-24 |
| 6968452 | Method of self-synchronization of configurable elements of a programmable unit | Robert Münch | 2005-11-22 |
| 6859869 | Data processing system | — | 2005-02-22 |
| 6728871 | Runtime configurable arithmetic and logic cell | Robert Münch | 2004-04-27 |
| 6721830 | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures | Robert Münch | 2004-04-13 |
| 6697979 | Method of repairing integrated circuits | Robert Münch | 2004-02-24 |
| 6687788 | Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.) | Robert Münch | 2004-02-03 |
| 6571381 | Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) | Robert Münch | 2003-05-27 |
| 6542998 | Method of self-synchronization of configurable elements of a programmable module | Robert Münch | 2003-04-01 |
| 6526520 | Method of self-synchronization of configurable elements of a programmable unit | Robert Münch | 2003-02-25 |
| 6513077 | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures | Robert Münch | 2003-01-28 |
| 6480937 | Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)-- | Robert Münch | 2002-11-12 |
| 6477643 | Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like) | Robert Münch | 2002-11-05 |
| 6425068 | UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (EPGAS) | Robert Münch | 2002-07-23 |
| 6405299 | Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity | Robert Münch | 2002-06-11 |
| 6338106 | I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures | Robert Münch | 2002-01-08 |
| 6119181 | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures | Robert Münch | 2000-09-12 |
| 6088795 | Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like) | Robert Münch | 2000-07-11 |
| 6081903 | Method of the self-synchronization of configurable elements of a programmable unit | Robert Münch | 2000-06-27 |