Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6718457 | Multiple-thread processor for threaded software applications | Marc Tremblay | 2004-04-06 |
| 6694347 | Switching method in a multi-threaded processor | Marc Tremblay, Gary R. Lauterbach, Joseph I. Chamdani | 2004-02-17 |
| 6615338 | Clustered architecture in a VLIW processor | Marc Tremblay | 2003-09-02 |
| 6542991 | Multiple-thread processor with single-thread interface shared among threads | Marc Tremblay, Gary R. Lauterbach, Joseph I. Chamdani | 2003-04-01 |
| 6529982 | Locking of computer resources | James M. O'Connor, Marc Tremblay | 2003-03-04 |
| 6507862 | Switching method in a multi-threaded processor | Marc Tremblay, Gary R. Lauterbach, Joseph I. Chamdani | 2003-01-14 |
| 6405300 | Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor | Marc Tremblay | 2002-06-11 |
| 6351808 | Vertically and horizontally threaded processor with multidimensional storage for storing thread data | Marc Tremblay, Gary R. Lauterbach, Joseph I. Chamdani | 2002-02-26 |
| 6343348 | Apparatus and method for optimizing die utilization and speed performance by register file splitting | Marc Tremblay | 2002-01-29 |
| 6341347 | Thread switch logic in a multiple-thread processor | Marc Tremblay, Gary R. Lauterbach, Joseph I. Chamdani | 2002-01-22 |
| 6304961 | Computer system and method for fetching a next instruction | Robert Yung, Kit S. Tam, Alfred Yeung | 2001-10-16 |
| 6233621 | System and method for space efficient hashcode allocation | — | 2001-05-15 |
| 6230230 | Elimination of traps and atomics in thread synchronization | James M. O'Connor, Marc Tremblay | 2001-05-08 |
| 6205543 | Efficient handling of a large register file for context switching | Marc Tremblay | 2001-03-20 |
| 6128721 | Temporary pipeline register file for a superpipelined superscalar processor | Robert Yung, Marc Tremblay | 2000-10-03 |
| 6021469 | Hardware virtual machine instruction processor | Marc Tremblay, James M. O'Connor | 2000-02-01 |
| 6014723 | Processor with accelerated array access bounds checking | Marc Tremblay, James M. O'Connor | 2000-01-11 |
| 5968157 | Locking of computer resources | James M. O'Connor, Marc Tremblay | 1999-10-19 |
| 5862376 | System and method for space and time efficient object locking | Guy L. Steele, Jr. | 1999-01-19 |
| 5845325 | Virtual address write back cache with address reassignment and cache block flush | William Loo, John E. Watkins, Robert B. Garner, Joseph P. Moran, III, William Shannon +1 more | 1998-12-01 |
| 5765157 | Computer system and method for executing threads of execution with reduced run-time memory space requirements | Timothy G. Lindholm | 1998-06-09 |
| 5761513 | System and method for exception handling in dynamically linked programs | Frank Yellin, Arthur van Hoff | 1998-06-02 |
| 5761670 | System and method for space efficient object locking using global and local locks | — | 1998-06-02 |
| 5727219 | Virtual input/output processor utilizing an interrupt handler | Thomas L. Lyon, Sun Den Chen, Leslie D. Kohn, Charles E. Narad, Robert Yung | 1998-03-10 |
| 5721868 | Rapid register file access by limiting access to a selectable register subset | Robert Yung, Michael R. Allen, Marc Tremblay | 1998-02-24 |