Issued Patents All Time
Showing 26–32 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6055610 | Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations | Kenneth K. Smith, Loren Staley | 2000-04-25 |
| 5995967 | Forming linked lists using content addressable memory | William R. Bryg, Joseph H. Hassoun | 1999-11-30 |
| 5860095 | Conflict cache having cache miscounters for a computer memory system | Dean Mulla | 1999-01-12 |
| 5696939 | Apparatus and method using a semaphore buffer for semaphore instructions | Dean Mulla | 1997-12-09 |
| 5664148 | Cache arrangement including coalescing buffer queue for non-cacheable data | Dean Mulla | 1997-09-02 |
| 5652859 | Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues | Dean Mulla | 1997-07-29 |
| 5493723 | Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits | Motti Beck, Ran Talmudi | 1996-02-20 |