Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7474546 | Hybrid dual match line architecture for content addressable memories and other data structures | Sagar V. Reddy, Ajay Bhatia | 2009-01-06 |
| 7203082 | Race condition improvements in dual match line architectures | Ajay Bhatia, Sanjay M. Wanzakhade | 2007-04-10 |
| 7200019 | Dual match line architecture for content addressable memories and other data structures | Ajay Bhatia, Sanjay M. Wanzakhade | 2007-04-03 |
| 6714464 | System and method for a self-calibrating sense-amplifier strobe | Ajay Bhatia, Michael C. Braganza, Shannon Vance Morton | 2004-03-30 |