Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7287237 | Aligned logic cell grid and interconnect routing architecture | — | 2007-10-23 |
| 7266787 | Method for optimising transistor performance in integrated circuits | Peter William Hughes, Trevor K. Monk | 2007-09-04 |
| 6714464 | System and method for a self-calibrating sense-amplifier strobe | Ajay Bhatia, Michael C. Braganza, Shashank Shastry | 2004-03-30 |