Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11412610 | Apparatus, system, and method for mitigating the swiss cheese effect in high-current circuit boards | Boris Reynov, David K. Owen, Steve Wilkinson, Jing Zhang | 2022-08-09 |
| 9958496 | Layer-layer registration coupon for printed circuit boards | Stephanie Moran, Karl Sauter | 2018-05-01 |
| 9354270 | Step drill test structure of layer depth sensing on printed circuit board | Stephanie Moran, Karl Sauter | 2016-05-31 |
| 8923007 | Multi-diameter unplugged component hole(s) on a printed circuit board (PCB) | Michael F. Sweeney, Jorge E. Martinez-Vargas, JR. | 2014-12-30 |
| 8431831 | Bond strength and interconnection in a via | Michael F. Sweeney, Jorge E. Martinez-Vargas, JR. | 2013-04-30 |
| 8237058 | Printed circuit board with low propagation skew between signal traces | Ricki Williams | 2012-08-07 |
| 7268302 | Low inductance mount for decoupling capacitors | Lawrence D. Smith | 2007-09-11 |
| 7162795 | Power distribution system with a dedicated power structure and a high performance voltage regulator | Larry D. Smith, Istvan Novak | 2007-01-16 |
| 6794581 | Method and apparatus for distributing power to integrated circuits | Larry D. Smith, Istvan Novak, Ali Hassanzadeh | 2004-09-21 |
| 6791846 | Power distribution system with a dedicated power structure and a high performance voltage regulator | Larry D. Smith, Istvan Novak | 2004-09-14 |
| 6760232 | Power distribution system having a dedicated power structure with apertures for mounting integrated circuit packages | Larry D. Smith, Ali Hassanzadeh | 2004-07-06 |
| 6727780 | Adding electrical resistance in series with bypass capacitors using annular resistors | Istvan Novak, Valerie St.Cyr, Merle Tetreault | 2004-04-27 |
| 6534872 | Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging | Han Y. Ko, Ali Hassanzadeh | 2003-03-18 |
| 6521846 | Method for assigning power and ground pins in array packages to enhance next level routing | Prabhansu Chakrabarti | 2003-02-18 |
| 6519747 | Method and apparatus for defining signal timing for an integrated circuit device | Satyanarayana Nishtala, Jayarama N. Shenoy, Tai-Yu Chou | 2003-02-11 |