Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9584305 | Deskew FIFO buffer with simplified initialization | Suwen Yang, Tarik Ono | 2017-02-28 |
| 9197397 | Flip-flop-based clock deskew circuit | Tarik Ono, Suwen Yang | 2015-11-24 |
| 9176878 | Filtering pre-fetch requests to reduce pre-fetching overhead | Tarik Ono | 2015-11-03 |
| 8683129 | Using speculative cache requests to reduce cache miss delays | Tarik Ono | 2014-03-25 |
| 8631265 | Synchronization circuit that facilitates multiple parallel reads and writes | Tarik Ono | 2014-01-14 |
| 8559576 | Adaptive synchronization circuit | Tarik Ono | 2013-10-15 |
| 8552779 | Synchronizer latch circuit that facilitates resolving metastability | Ian W. Jones, Suwen Yang, Hetal N. Gaywala, Robert J. Drost | 2013-10-08 |
| 8179208 | Interconnect for surfing circuits | Robert J. Drost, Alex Chow, Suwen Yang | 2012-05-15 |
| 7333527 | EMI reduction using tunable delay lines | Robert J. Bosnyak, Stuart A. Ridgway | 2008-02-19 |
| 7076680 | Method and apparatus for providing skew compensation using a self-timed source-synchronous network | — | 2006-07-11 |
| 7073086 | System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit | — | 2006-07-04 |
| 6768342 | Surfing logic pipelines | Brian Winters | 2004-07-27 |
| 6703949 | Method and apparatus for facilitating balanced bundles of electrical signals | — | 2004-03-09 |
| 6694389 | Method and apparatus for data flow analysis | William S. Coates | 2004-02-17 |
| 6686854 | Method and apparatus for latching data based on a predetermined number of signal line transitions | — | 2004-02-03 |
| 6621427 | Method and apparatus for implementing a doubly balanced code | — | 2003-09-16 |
| 6486721 | Latch control circuit for crossing clock domains | Josephus C. Ebergen | 2002-11-26 |
| 4868776 | Fast fourier transform architecture using hybrid n-bit-serial arithmetic | Joseph H. Gray, Lars Jorgensen | 1989-09-19 |
| 4768159 | Squared-radix discrete Fourier transform | Joseph H. Gray | 1988-08-30 |