Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5892970 | Multiprocessing system configured to perform efficient block copy operations | — | 1999-04-06 |
| 5893150 | Efficient allocation of cache memory space in a computer system | Mark D. Hill | 1999-04-06 |
| 5893160 | Deterministic distributed multi-cache coherence method and system | Paul N. Loewenstein | 1999-04-06 |
| 5887138 | Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes | Paul N. Loewenstein | 1999-03-23 |
| 5881303 | Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode | Paul N. Loewenstein, Monica C. Wong-Chan | 1999-03-09 |
| 5878268 | Multiprocessing system configured to store coherency state within multiple subnodes of a processing node | — | 1999-03-02 |
| 5873117 | Method and apparatus for a directory-less memory access protocol in a distributed shared memory computer system | Mark D. Hill | 1999-02-16 |
| 5864671 | Hybrid memory access protocol for servicing memory access request by ascertaining whether the memory block is currently cached in determining which protocols to be used | Mark D. Hill | 1999-01-26 |
| 5862357 | Hierarchical SMP computer system | Mark D. Hill | 1999-01-19 |
| 5862316 | Multiprocessing system having coherency-related error logging capabilities | John R. Catenzaro, William A. Nesheim, Monica C. Wong-Chan, Robert C. Zak, Paul N. Loewenstein | 1999-01-19 |
| 5860109 | Methods and apparatus for a coherence transformer for connecting computer system coherence domains | Mark D. Hill, David A. Wood | 1999-01-12 |
| 5860159 | Multiprocessing system including an apparatus for optimizing spin--lock operations | — | 1999-01-12 |
| 5852716 | Split-SMP computer system with local domains and a top repeater that distinguishes local and global transactions | — | 1998-12-22 |
| 5848254 | Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space | — | 1998-12-08 |
| 5842026 | Interrupt transfer management process and system for a multi-processor environment | Monica C. Wong-Chan | 1998-11-24 |
| 5835906 | Methods and apparatus for sharing stored data objects in a computer system | Mark D. Hill | 1998-11-10 |
| 5829033 | Optimizing responses in a coherent distributed electronic system including a computer system | Ashok Singhal, Bjorn O. Liencres | 1998-10-27 |
| 5829034 | Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains | Mark D. Hill, David A. Wood | 1998-10-27 |
| 5802563 | Efficient storage of data in computer system with multiple cache levels | Mark D. Hill | 1998-09-01 |
| 5802566 | Method and system for predicting addresses and prefetching data into a cache memory | — | 1998-09-01 |
| 5796605 | Extended symmetrical multiprocessor address mapping | — | 1998-08-18 |
| 5778427 | Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure | Ashok Singhal | 1998-07-07 |
| 5754877 | Extended symmetrical multiprocessor architecture | Mark D. Hill | 1998-05-19 |
| 5749095 | Multiprocessing system configured to perform efficient write operations | — | 1998-05-05 |
| 5734922 | Multiprocessing system configured to detect and efficiently provide for migratory data access patterns | Mark D. Hill | 1998-03-31 |