Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7533212 | System memory board subsystem using DRAM with integrated high speed point to point links | Drew G. Doblar, Gabriel Risk | 2009-05-12 |
| 7409491 | System memory board subsystem using DRAM with stacked dedicated high speed point to point links | Drew G. Doblar, Gabriel Risk | 2008-08-05 |
| 7352641 | Dynamic memory throttling for power and thermal limitations | — | 2008-04-01 |
| 7334149 | Clock distribution architecture with spread spectrum | — | 2008-02-19 |
| 7233538 | Variable memory refresh rate for DRAM | Robert C. Zak | 2007-06-19 |
| 7064994 | Dynamic memory throttling for power and thermal limitations | — | 2006-06-20 |
| 7051235 | Clock distribution architecture having clock and power failure protection | — | 2006-05-23 |
| 7043655 | Redundant clock synthesizer | — | 2006-05-09 |
| 6996686 | Memory subsystem including memory modules having multiple banks | Drew G. Doblar | 2006-02-07 |
| 6930904 | Circuit topology for high-speed memory access | — | 2005-08-16 |
| 6853594 | Double data rate (DDR) data strobe receiver | Jyh-Ming Jong | 2005-02-08 |
| 6737892 | Method and apparatus for detecting valid clock signals at a clock receiver circuit | Jyh-Ming Jong, Prabhansu Chakrabarti, Leo Yuan | 2004-05-18 |
| 6690191 | Bi-directional output buffer | Jyh-Ming Jong | 2004-02-10 |
| 6542026 | Apparatus for on-chip reference voltage generator for receivers in high speed single-ended data link | Jyh-Ming Jong, Prabhansu Chakrabarti, Leo Yuan | 2003-04-01 |
| 6512704 | Data strobe receiver | Jyh-Ming Jong, Lee A. Warner, Jurgen Schulz | 2003-01-28 |
| 6462593 | Compensation circuit for low phase offset for phase-locked loops | Drew G. Doblar | 2002-10-08 |